1. Field of the Invention
The invention relates generally to fault injection as applied to hardware and software system testing and more specifically relates to an enhanced boundary scan cell architecture and method for use thereof to provide controllable fault injection in a system board under test.
2. Discussion of Related Art
In the design of electronic systems, it is generally known in the art that a system should be tested by simulating fault conditions to verify proper operation of the system in response to such simulated fault conditions. In general, a system includes discrete electronic components mounted on a printed circuit board (PCB) and interconnected by conductive signal paths (traces) etched onto and into the printed circuit board. Such signal paths are conductive material affixed to the surface of the printed circuit board or embedded within layers of the printed circuit board.
Interconnecting such signal paths between multiple layers requires conductive material extending between two such conductive signal paths on different layers of the printed circuit board. Such multiplayer interconnecting signal pads are typically referred to as xe2x80x9cvias.xe2x80x9d
As the electronics industry has evolved, the density of pins or pads on integrated circuits (ICs) used to connect circuitry components to conductive paths on the PCB has risen dramatically. Further, the density of the interconnecting signal paths and vias on the PCB has similarly increased. Such increases in density have required corresponding decreases in the physical dimensions of pins or pads of ICs mounted on a PCB as well as corresponding decreases in the physical dimensions of signal paths and vias on the various layers of the printed circuit board.
The goal of being able to verify the system in an operational mode requires some ability to emulate a system fault condition. Using simulation techniques requires that accurate models be developed for each of the complex devices often present in present day printed circuit boards. The ability and cost to develop the required models is often beyond the capabilities of many companies. In addition, running a simulation of a complete system for testing of such fault conditions can require an enormous amount of computational time and resources.
In view of the problems with simulation of such fault conditions, it is common practice to run the actual system and physically inject fault conditions so as to observe the result in operation of the system. The fault is injected by physical contact between a test probe and a conductive point on the system board (i.e., a signal trace or via or a connector pad on a particular circuit component). However, the interconnect densities of systems boards has increased and the physical dimensions of signal traces, vias and connector pads on integrated circuit components have correspondingly decreased. The ability to make accurate physical contact with signals on a printed circuit board for purposes of injecting a fault signal has become more difficult if not impossible in view of these factors. Further, there is a concern that the system board and/or components on the board may be damaged due to the length of time that a signal may be forced or overdriven to inject a desired fault condition. Lastly, there is a desire to automate the test process as much as possible to improve the quality and accuracy of the test as well as reduce the costs to perform the test.
Another approach entails the use of boundary scan register features within most present-day integrated circuit designs to inject faults on global signals distributed throughout the PCB system under test. In general, boundary scan features within present-day integrated circuits allow for application of signals to the input and output signal pads of an integrated circuit package by shifting control and data information into individual devices of the system and controlling or observing output and input of the components independent of normal system operation.
Various problems arise in attempting to use boundary scan features that support fault injection as presently embodied within most integrated circuits. First, all pins must be faulted in the same state. In other words, if a desired fault is a xe2x80x9cstuck at 1xe2x80x9d fault condition, all signal paths will be forced to simulate the stuck at 1 fault conditions. Similarly, to simulate a xe2x80x9cstuck at 0xe2x80x9d fault condition, all signals will simulate the stuck at 0 fault condition due to the use of present boundary scan features. It is not possible with present boundary scan register designs to test some pins for stuck at 1 injected faults while testing other pins for stuck at 0 faults. Further, it is riot possible with present boundary scan features to test some pins for injected faults without necessarily affecting all pins of ICs with boundary scan features on the PCB. Further, present techniques for using boundary scan features of ICs on a PCB to perform fault injection require a minimum of one additional signal to be routed to all boundary scan elements within ICs of the PCB. As many as three additional signals may be required in many common scenarios.
In at least one known variation to the approach of using present boundary scan features to perform fault injection testing, individual pins/pads of an IC may be individually controlled. However, this known approach adds several combinatorial gates and a latch to each boundary scan register structure and at least one additional signal path globally routed to all boundary scan registers of ICs in the PCB system. This added complexity can dramatically increase cost and complexity of the system. Another approach adds several logic gates and a latch to the complement of circuits in a standard boundary scan register structure. As above, this added structure is unduly complex.
It is evident from the above discussion that a need exists for improved architecture for use of boundary scan features to aid in fault injection testing of a PCB system design.
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing structures and methods for using an enhanced boundary scan circuit design to provide flexible fault injection testing capability. More specifically, the structure of the present invention adds two 2-input logic gates (an OR gate and an AND gate) to each boundary scan register structure of each pin of each IC on the PCB plus one globally routed signal. Additional special instructions issued to the test access port (TAP) portion of the IC modify control of the existing boundary scan register structure to enhance its operation in conjunction with the added gates and global signal of the present invention. The structure of the present invention adds minimal complexity to the boundary scan structure of the ICs of the PCB as compared to prior techniques. A second exemplary preferred embodiment further provides that an additional XOR logic gate may be added to permit selective complementing of an inbound system signal to serve as the injected fault.
Associated methods of use of the structure provide for issuance of newly defined special instructions to allow flexible definition of fault injection test sequences whereby pins of ICs on the PCB may be individual controlled to provide a stuck at 1 condition, a stuck at 0 condition or may operate normally in accordance with the design of the IC. The additional special instructions operate the enhanced boundary scan register structure to enable use of the capture flip-flop (CAP_FF) as a signal to enable selective application of the pre-loaded stuck-at fault to the output pad or to enable normal operation (i.e., application of the standard system output signal to the output pad. The structures and methods of the present invention add minimal complexity to the standard boundary scan registers of the IC while permitting enhanced flexibility in individually selecting controlled application of a stuck-at fault on each output pad of an IC.
A first feature of the invention therefore provides for an improved boundary scan cell, the improvement comprising: an enhanced boundary scan enable signal to controllably enable enhanced operation of the boundary scan cell; an AND gate having an output and having a first input coupled to the output of a capture flip-flop of the boundary scan cell and having a second input coupled to the enhanced boundary scan enable signal; and an OR gate having a first input coupled to a boundary scan mode signal of the boundary scan cell and having a second input coupled to the output of the AND gate and having an output coupled to the selection input of a multiplexer of the boundary scan cell for selectively applying the output of a hold latch of the boundary scan cell to an outbound operational signal of the boundary scan cell.
Another aspect of the invention further provides a second AND gate having an output and having a first input coupled to the enhanced boundary scan enable signal and having a second input coupled to an inbound operational signal of the boundary scan cell; and an XOR gate having its output selectively coupled through the multiplexer to the outbound operational signal path and having a first input coupled to the output of the hold latch and having a second input coupled the output of the second AND gate whereby the XOR gate is operable to selectively compliment the inbound operational signal for application to the multiplexer based on the signal in the hold latch.
Another feature of the invention provides for a boundary scan cell comprising: a first signal pathway selectively configured to apply an inbound operational signal to an outbound operational signal path; and a second signal path for selectively applying a predetermined fault signal to the outbound operational signal path.
Another aspect of the invention further provides an enhanced boundary scan enable signal for selectively enabling operation of the second signal pathway and disabling operation of the first signal pathway.
Another aspect of the invention further provides a third signal pathway selectively configured to apply an inbound scan signal to an outbound scan signal path.
Another aspect of the invention further provides a first enable signal for selectively enabling operation of the second signal pathway and disabling operation of the first signal pathway; and a second enable signal for selectively enabling operation of the third signal pathway and for disabling operation of the first signal pathway and for disabling operation of the second signal pathway.
Another feature of the invention provides a method for injecting a fault condition on an I/O signal pad of the integrated circuit comprising the steps of: loading a fault signal representing the fault condition into the hold latch of the boundary scan register associated with the I/O signal pad; loading the capture flip-flop of the boundary scan register with a cell enable signal value; applying a global enable signal to an enhanced operation enable input of the boundary scan register; and applying the fault signal to the I/O signal pad in response to the combination of the application of the global enable signal to the enhanced operation enable input and the loading of the cell enable signal in the capture flip-flop.
Another aspect of the invention further provides for complimenting the fault signal prior to applying the fault signal to the I/O pad.
Another aspect of the invention further provides that the step of loading a fault signal comprises the step of: applying a preload instruction to the TAP controller of the integrated circuit.
Another aspect of the invention further provides that the step of applying a global enable signal comprises the step of applying a first instruction to the TAP controller, and that the step of loading the capture flip-flop comprises the step of applying a second instruction to the TAP controller.